I'm surprised BBC is not only willing to make custom hardware, but custom RTL design as well.
I'm curious what the failure rate of the FPGA will be, I mean they are more susceptible to soft errors than CPUs or ASICs. Maybe BBC will fund making a custom ASIC :-) Well I see two systems, maybe they are redundant that way.
Why not make the project open source? Put it up on github.
I would doubt an ASIC would be worth it, giving the number of organisations needing this CODEC would be relatively low. An ASIC run is expensive and even more expensive if there is subsequent error in the design.
FPGA makes sense for this application. It can always be re-flashed.
They should at least enable the SEU mitigation circuit, which repeatedly performs CRC of the configuration data. Have it reboot if it detects an error. Maybe they already do this.
I'm surprised BBC is not only willing to make custom hardware, but custom RTL design as well.
I'm curious what the failure rate of the FPGA will be, I mean they are more susceptible to soft errors than CPUs or ASICs. Maybe BBC will fund making a custom ASIC :-) Well I see two systems, maybe they are redundant that way.
Why not make the project open source? Put it up on github.